Yield-Aware Power, Performance, and Area Optimization
Intrinsic scaling — the shrink-driven gains chipmakers have relied on for decades — is running out of headroom, just as AI's demand for better chips keeps climbing. Most of the industry is using AI to make the existing design process faster. DeepWeave's products represent a paradigm shift using AI-native design-technology co-optimization to generate fundamentally better designs.
Incumbent EDA tools are stuck tuning one step at a time within a toolchain that's already notoriously complex and difficult to work within — a structural limit. Most AI EDA startups focus on designer productivity — we do too, but we also make PPA a first-class objective — overcoming two major headwinds today:
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Loom reasons across power, performance, area, and yield — inside the tools chip teams already use, with no new toolchain, no new PDK, and no disrupted signoff. Loom is already delivering results with design partners, including GlobalFoundries.
Backed by leading AI and semiconductor investors, built by veteran EDA and AI engineers.
Engaged with design partners spanning both advanced and mature process nodes.
Leadership Team
Unni Narayanan Founder and CEO
Unni is a former Senior Director of Engineering at Google, where he led Engineering and Product for Search Apps and later the Assistant Engineering team behind the Gemini-based LLM platform for Google Home. Before Google, Unni spent a decade as a serial entrepreneur — and before that, created Intel's first schematic power estimation tool, ASPEN. He holds a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign (dissertation: Low Power Logic Synthesis) and has published 10 EDA research papers.
David Pan Founder and CTO
David is the Silicon Labs Endowed Chair Professor at UT Austin. He is a global leader in EDA, especially AI for chip design, backend design, and DFM. He has published over 500 research papers and 10 US patents, and received the SRC Technical Excellence Award and over 20 Best Paper Awards. He has advised Google X, DeepMind, and startups. He has worked with many top semiconductor, fabless, and EDA companies. He is a Fellow of ACM, IEEE, and SPIE.
Jason Cong Advisor
Jason is the Volgenau Chair for Engineering Excellence in the UCLA Computer Science Department (with joint appointment in ECE), the Director of Center for Domain-Specific Computing, and the director of VLSI Architecture, Synthesis, and Technology (VAST) Lab. He served as UCLA CS Department Chair from 2005 to 2008. He was elected to an IEEE Fellow in 2000, an ACM Fellow in 2008, a member of the National Academy of Engineering in 2017, and a Fellow of the National Academy of Inventors in 2020. He is a serial entrepreneur and won the Phil Kaufman Award, i.e., the EDA "Nobel" Prize.
Rajeev Madhavan Advisor
Rajeev served as Magma's Chairman and CEO from when he co-founded the company in 1997 through its acquisition by Synopsys in February 2012 for $580 million. Magma was listed on Nasdaq in 2001 and was ranked as the 2nd fastest growing Technology Company in 2005 by Forbes. Magma provided core infrastructure software to mobile pioneers such as Apple, Qualcomm, and Samsung, which was used to design the core processors at the heart of the smartphone era. Today, Rajeev is a highly regarded Venture Capitalist (with many successful EDA investments) at Radiant Capital.
Andrew Tan Advisor
Andrew is a Managing Director at Salience Capital and A&E Investments, where he invests in early-stage AI and deep-tech startups, and the Co-Founder of HiTA AI. He has been an early backer of companies including RadixArk, Nace AI, NeoCognition, Virtue AI, Pokee AI, and EPIC Microsystems, where he also serves on the board. Earlier in his career, Andrew worked at Google, later held product management leadership roles at Katana Graph, and was an Investment Manager at Capstone Partners. He holds a Master of Science and Bachelor of Science in Electrical and Computer Engineering from Carnegie Mellon University.
We're Hiring
Join Us
We're building one of the most consequential AI companies of the decade — revolutionizing how semiconductors and chips are designed. DeepWeave Loom is live today, backed by pre-seed investment and a design partnership with GlobalFoundries — and we're just getting started. We're hiring across all three areas below, at multiple levels of seniority. If you're drawn to hard problems at the intersection of AI and the physical world, and you want your work to matter, we'd love to hear from you.
Send your resume to
Multiple Openings
CAD / EDA Engineer
We're looking for software engineers who understand the nuances of the IC implementation flow — particularly backend.
BS/MS/PhD in Electrical / Computer Engineering, Computer Science, or related field
Hands-on R&D experience with any of the following areas: physical design / verification, characterization, modeling, or synthesis.
Familiarity with industry-standard EDA tools and methodologies
Experience at advanced process nodes (7nm and below) a strong plus
Full-stack expertise a strong plus
Multiple Openings
Forward Deployment Engineer
You'll be the technical bridge between our platform and our customers — helping design teams deploy our products into their flows, troubleshoot issues, and get the most out of holistic PPA optimization. Software development is part of this role.
BS/MS in Electrical / Computer Engineering, Computer Science, or related field
Prior experience in a technical customer-facing role in EDA or the semiconductor industry
Strong software development skills
Strong working knowledge of IC design flows, methodologies, and tapeout processes
Excellent communication skills; comfortable bridging engineering and business requirements
Multiple Openings
AI / ML Engineer
We apply cutting-edge machine learning — including reinforcement learning, generative models, and large language models — to one of the hardest optimization problems in engineering. You'll work at the frontier of both fields.
MS/PhD in Electrical / Computer Engineering, Computer Science, Mathematics, or related field
Deep expertise in one or more of: reinforcement learning, diffusion models, LLMs
Strong proficiency in PyTorch or equivalent deep learning frameworks
Experience with graph neural networks or structured/combinatorial optimization a plus
Interest in applying AI to real-world engineering domains
For half a century, progress in chips ran on a simple promise: transistors would shrink, everything would get faster, and the entire industry could set its clock by it. That promise is running out. Shrinking silicon no longer delivers the power, performance, and area gains it once did — and it is failing precisely as AI’s hunger for better chips has reached a level the world has never seen.
When manufacturing stops carrying the gains, they have to come from somewhere. They have to come from the design itself: how intelligently a chip is shaped around the work it has to do. This is the most valuable unsolved problem in technology today. And the industry is meeting it with the wrong tools.
One camp is teaching AI to do the engineer’s job a little faster. It automates the tasks humans already do, while the chip itself stays exactly the same. The other has spent decades perfecting tools that tune the design one narrow stage at a time, then bolted AI on top as a convenience. The moment is here, and no one is meeting it.
Neither is reaching for the prize that actually matters: a fundamentally better chip.
DeepWeave was built to meet it. We are not here to make the old process faster, or to add another layer to a flow that was never designed for this era. We are here to change what the design itself can achieve — to reach power, performance, and area outcomes that step-by-step tuning and hand-crafted effort simply cannot reach, through deeper design-technology co-optimization (DTCO) between chip architecture and manufacturing constraints. That gap is DeepWeave’s focus. Loom, our first product, attacks backend design holistically and from first principles, exploring a space of tradeoffs far larger than any team could by hand, and it does it inside the flows chip teams already trust: no new toolchain, no new PDK, no disrupted signoff.
This is a fundamentally new category of optimization — a paradigm shift — and it is only the beginning. It is the first step toward AI-native backend design intelligence: systems that reason across the entire design the way the best engineers only wish they could. The next era of better chips will not be won by doing the old work faster. It will be won by doing what was never possible. That is the work we are here to do.
Why DeepWeave Is Different
We will use AI to do what humans can’t — not just what they do, faster.
Most AI tools attempt to make engineers faster at the tasks they already do, and Loom makes teams more productive too. But that is the floor, not the ceiling. Our real aim is to reach chip outcomes that no amount of faster hand-tuning could ever deliver: less power, more performance, less area.
We rethought the problem holistically instead of bolting AI onto one small task.
Today’s tools were built to optimize one narrow task at a time. Loom starts over from first principles, reasoning holistically across the entire backend-design problem at once.
We reach outcomes teams cannot reach by hand.
Even the best design teams are limited by how many tradeoffs a person can hold and explore. Loom is built to push past that limit today. Our roadmap points toward AI-native design intelligence that reasons across the entire problem.
Contact Us
July 14, 2026
DeepWeave Partners with GlobalFoundries
DeepWeave is pleased to announce a collaboration with GlobalFoundries, a leading global semiconductor foundry. As AI reshapes semiconductor design, customers are looking for new ways to improve performance and efficiency without increasing complexity — and the collaboration is focused on evaluating how DeepWeave Loom's holistic PPA optimization can help designers extract additional value from GF platforms while preserving the proven workflows they rely on today.
“As AI reshapes semiconductor design, customers are looking for new ways to improve performance and efficiency without increasing complexity. Through our collaboration with DeepWeave, we are evaluating innovative optimization technologies that can help designers extract additional value from GF platforms while preserving the proven workflows they rely on today. Together, we are expanding the possibilities for more efficient chip design and faster innovation.”
Haritez Narisetty, Senior Director of Scalable Solutions, GlobalFoundries
Working closely with GlobalFoundries' technology and design enablement teams, DeepWeave is evaluating Loom across a range of process nodes and design styles relevant to GlobalFoundries' customer base, ensuring the platform addresses real-world foundry and design constraints while expanding the possibilities for more efficient chip design and faster innovation.
If your organization is interested in exploring a partnership with DeepWeave, please contact us.
DeepWeave today announced the availability of DeepWeave Loom™, a platform that augments the backend design stage of IC implementation. DeepWeave Loom works alongside your existing VLSI design flow and toolchain, attacking PPA optimization holistically from first principles — without requiring changes to your design methodology or EDA environment.
DeepWeave Loom is designed to address a challenge that has become increasingly critical as chip complexity grows and traditional manufacturing-driven scaling delivers fewer gains: extracting meaningful power, performance, and area improvements within the backend design stage. Where traditional point tools operate locally on one stage of the flow, DeepWeave Loom reasons holistically over the design — integrating design and technology constraints (DTCO) more aggressively — and identifies opportunities conventional approaches miss.
Early access customers have reported improvements across all three PPA dimensions. DeepWeave is now accepting requests for evaluation access from qualifying design teams.
DeepWeave Raises Pre-Seed Investment to Advance AI-Native Backend Design
DeepWeave has raised pre-seed investment to accelerate its mission to transform semiconductor backend design — advancing holistic PPA optimization today while paving the way toward AI-native backend design intelligence over time. The financing was led by Root Ventures, with participation from SciFi Ventures, 10One10, A&E Investments, Homebrew, Growth Enjin Partners, and several high-profile Silicon Valley AI angel investors.
We are grateful for the support of investors who share our belief that power, performance, and area optimization represents one of the most consequential opportunities in chip design. Their backing will help us expand our engineering team, advance the DeepWeave Loom platform, and deepen collaboration with early design partners.
“Every chip company fights the same war: squeezing power, performance, and area out of tools that hit their ceiling years ago. DeepWeave isn’t bolting AI onto legacy EDA; they’re rethinking backend design entirely. No one else is approaching the problem this way — it will unlock categories of designs that previously weren’t possible,” said Chrissy Meyer of Root Ventures.
“The opportunity to apply AI to PPA optimization is both technically ambitious and commercially significant,” said Max Levchin, founder of Affirm and PayPal. “Unni and David bring the experience, vision, and persistence needed to build something truly important for the future of chip design.”
We are building a world-class team across CAD/EDA engineering, AI and machine learning research, and customer engineering. Interested candidates are encouraged to visit our Careers page or send a resume directly to .
We're here to help you understand how DeepWeave Loom works and whether it's the right fit for your design environment. Whether you have technical questions, want to explore a pilot, or are ready to schedule a demo — our team is ready to connect.
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